1.
Your statement:
"In a majority of applications the positive effect from faster memory is negated by the limited bandwidth of the front-side bus that connects the chipset's North Bridge with the CPU. "
Is utterly false -- you would need to explain why using the same memory and timings applications scale with increasing CPU speed (via multiplier), i.e. X6800>E6700>E6600. This is not a bottleneck at the CPU issue, rather increased misrate/cache issue.
Jerry
"In a majority of applications the positive effect from faster memory is negated by the limited bandwidth of the front-side bus that connects the chipset's North Bridge with the CPU. "
Is utterly false -- you would need to explain why using the same memory and timings applications scale with increasing CPU speed (via multiplier), i.e. X6800>E6700>E6600. This is not a bottleneck at the CPU issue, rather increased misrate/cache issue.
Jerry
[Posted by: Jerry A. | Date: 09/08/06 08:00:57 PM]





