Advanced Micro Devices may offer gamers something, which significantly boosts performance of single-threaded games with its new central processing units (CPUs) in socket AM2 form-factor, the sources claim.
In April 2006 some rumors emerged that AMD was working on the technology designed to boost performance of single-threaded applications on multi-core processors. According to certain sources familiar with AMD plans, the company is going to offer their own technology that will work in an opposite way to what Intel Hyper-Threading does: it increases performance of dual-core chips in single-threaded applications. If the latter splits resources of a single physical processor core, then AMD’s new know-how will allow combining the resources of the two physical cores to speed up the processing of tasks that work in the most optimal way on single-core CPUs, according to sources.
According to sources, it would be possible to double the number of decoders this way so that the “combined: CPU will process 6 instructions per clock cycle. This thing only can become a pretty decent response to Conroe processors and it should be expected that this technology would debut closer to July 24, the day of the Intel Core 2 for desktops launch. But the feature should require synchronization of chips’ L1 cache in general along with some other capabilities. Perhaps, the new technology will simply overclock the processor and disable the second core in certain situations.
The corresponding functionality has already been built into dual-core Athlon 64 X2 processors for Socket AM2 form-factor, the sources claim. To activate it customers will “only need to update the processor driver and the mainboard BIOS,” they say. Microsoft Corp. will reportedly even release a corresponding patch for the operating systems that will allow recognizing two cores of the Athlon 64 X2 as a single one.
According to sources and alleged preliminary test results, the CPU will be able to switch into this “combined” mode dynamically, depending on the type of the application. There is no secret that a lot of tasks still benefit from single-core CPUs more than they would from the dual-core processors working at lower nominal frequencies.
It is remarkable that at the same time AMD will also push forward their 4x4 platform for enthusiasts who cannot imagine their life without multi-tasking and absolutely extreme performance. It seems that these two completely different initiatives will be positioned in different market niches. At least the owners of socket AM2 Athlon 64 X2 will be able to put two cores into a single virtual one for free if we do not consider downloading the new BIOS and OS driver that much of a trouble.
AMD did not comment on the news-story.
Comments currently: 19
Discussion started: 06/22/06 05:13:21 PM
Latest comment: 08/25/06 02:12:35 PM
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[1-13]
1.
only time will tell. but I just get this feeling that AMD is scrambling to get a decent foe to conroe w/out much success.
[Posted by: larciel | Date: 06/22/06 05:13:21 PM]
2.
Sounds like marketing hype or bullshit ...
How does it gonna handle CONDITIONAL BRANCHES and STACK BASED CALLS?
How do you "reverse" thread those?
For example:
mov eax, data1
push eax
call processA
pop eax
cmp eax, data2
jle pointB
push eax
call processB
pop eax
pointB: ret
How is it gonna transverse from PointB when it has to wait for eax? Even this piece of simple x86 code will prove diificult for OOO execution engines...
[Posted by: NooB | Date: 06/23/06 01:58:30 AM]
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Duh. its called speculative execution. Go read up bud.
[Posted by: DooB | Date: 06/23/06 11:57:11 AM]
Your piece of code means that you have no idea how CPUs work. You probably have a computer science degree but not a computer/electrical engineering degree.
CPUs are far more complicated than that and your code proves nothing.
[Posted by: Shorman | Date: 06/23/06 04:23:05 PM]
3.
Who cares?
When something has NO sense, it still has WAY MORE sense then this reverse thingy...
[Posted by: 1234 | Date: 06/23/06 03:45:47 AM]
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Time will tell if this reverse thingy worth it or not.
I believe it will be a big hit if this news story is correct.
[Posted by: Shorman | Date: 06/23/06 04:25:08 PM]
4.
For this thingy to work requires shared registers and shared cache. Current AMD processors do NOT have this...
[Posted by: AMD bullshitting again | Date: 06/23/06 07:01:56 AM]
5.
Yeah, it's interesting AMD talks 4x4 at Computex, yet all the MOBO mfgs, et. al., are caught off guard and a kind of like - AMD what?
Didn't this rumor make it around about 9-12 months ago with almost the exact same tag line - hyperthreading in reverse or reverse hyperthreading?
Intel's Hyperthreading approach, it can be argued is a direct response to Netburst not being incredibly efficient in single-threaded performance. But viewed in the lense of history, HT with its two logical processors, is truly a baby-dual core and moved the mainstream community to the dual-core doorstep. And neither AMD nor Intel is arguing against the idea that dual/multi core is the future.
As pointed out above, isn't going the opposite way kinda like trying to capture car exhaust, push it back thru the engine, and expecting to end up with gasoline?
[Posted by: mark1 | Date: 06/23/06 10:36:47 AM]
6.
Wow!!!
You fanbois sure look like engineers to me!!
replies2-4 why don't you team up and design your own processors with all your knowledge? or maybe join intel? (you're prolly working for them already... lol)
biased dumb set of pussy-less dorks...
[Posted by: Lost | Date: 06/23/06 10:42:09 AM]
7.
Go back home now, Hector prepared something to eat.
[Posted by: 1234 | Date: 06/23/06 03:01:47 PM]
8.
If you guys read the article carefully and read the similar one at theinquirer.net then you will know that this technology makes sense.
Each CPU has different FPU units. three in each AMD core I guess. more FPU units mean faster processing becuase you can do more instructions per cycle. when a thread gets nasty and consumes a lot of power from one CPU then the system will assign the available FPU units in the other core to the busy core.
does not sound complicated and hard to understand for me.
if more FPU units in the same core do not mean more performance then why the hell would AMD and Intel put more than one unit in each core?
for a programmer this technology does not make sense, but for an engineer it makes a lot of sense.
Now go and put that piece of code you wrote in a trash bin.
[Posted by: Shorman | Date: 06/23/06 04:19:50 PM]
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A core has multiple FPU units because it can process multiple instructions in parallel (and out of order).
The thing is, it happens on one core, meaning the instructions all share the same register file and the same OOO logic. That means one instruction can be assigned to either one of the FPU units with no penalty.
However, doing the same between cores is a radically different thing. At the very minimum, you need to transfer the instructions to the other core, and transfer the resulting register changes back to the first core. Then you need the logic to keep track of which instructions are currently being processed on the other core, as well as when you can expect to see the result. This is already being done inside each individual core, where latency isn't a factor.
The key point here is that it is only an advantage if you can find instructions that are independent, and assign them to a FPU unit each. However, independent instructions are hard to come by. Sooner or later, the result *will* be needed, which means you get a dependence. If the result you need is residing on a different core, you have to wait *a long* time for it to get back to you. That means *lower* efficiency, not higher.
If you have multiple threads, this works fine, because the two cores do not attempt to interleave or mix instruction. Each core is assigned one thread exclusively, and so, it doesn't matter how long it'd take to get a result from instructions processed on the other core.
Splitting a thread across multiple cores is different, because you constantly need access to previously processed instructions, to act as input for new ones. That's ok on single cores with multiple FPU units, because they're all close to the register file, so their results can be returned quickly. But having to send it across a hypertransport link from core A to core B would introduce a delay that'd really hurt performance.
Actually you got it wrong. For a programmer this makes sense, but for an engineer it doesn't.
[Posted by: Jalf | Date: 06/25/06 07:15:27 AM]
Actually it may be good idea. At least with K8 architecture. Remember that both cores communicate with each other via some 'direct-connect-request-bus' and memory controler is there too. IMHO it is only matter of adding more logic to this part and make it more like Ati thread dispatch arbiter. There will be latency, no doubt, but using twice resources may finally increase performance about 50% in single-threaded appl.
Excuse my english. Im not native.
[Posted by: Mali | Date: 06/27/06 11:52:04 AM]
9.
I had the impression that for most software this would do nothing or be barely noticable, but in some, notably single threated games, would see an improvement. How much would vary from game to game. I can imagine though that this would have greater impact in a quad core than a dual core.
[Posted by: AlanSymes | Date: 06/23/06 07:36:27 PM]
10.
ewrewr
[Posted by: rewr | Date: 06/24/06 11:50:19 AM]
11.
Its an interessting approach, but it will probably not make that much impact until you get alot of cores, like the 4x4 platform with 8 cores. Then it will probably make some difference.
[Posted by: Silver | Date: 06/24/06 03:11:46 PM]
12.
If this is indeed the case, then an AM2 CPU would be waaay more than a simple transfer of the existing core to a new socket. S939 dual-cores are joined at the SRQ, whereas the "reverse hyperthreading" thing would require that the two cores were also joined in the schedulers, decoders, and register files. Basically it would be a single-core chip that could be split in half to form a dual-core chip. Not beyond the realm of possibility, but it would basically be a complete core re-design.
[Posted by: Cynic | Date: 06/25/06 09:19:04 PM]
13.
Those are x86 assembly codes.. Don't you recognize?
My code demonstrates that you need shared resources such as registers and caches for this "duplexing" thingy to work... Note the stack (shared cache required), conditional jump (shared flag register required), eax operation (shared accumulator register required), etc... Heck it also needs a shared PC/IP and SP (Program Counter/Instruction Pointer and Stack Pointer)...
Currently all AMD dual cores have separate registers and separate caches!
AMD=Always Minds Dumber.
[Posted by: NooB | Date: 06/26/06 03:10:55 AM]
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Intel = Idiots 'n' terribly empowered lammers :D
Nice flame.
[Posted by: Mali | Date: 06/28/06 07:36:09 AM]
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