Intel processors from the Nehalem generation that are scheduled to appear in H2 2008 will exist in two modifications: Socket H (LGA 715) and Socket B (LGA 1336). This difference in the number of pins is determined by Intel’s decision to offer two CPU modifications: with the integrated three-channel memory controller and without it.

According to The Inquirer, Intel is not hurrying to introduce integrated memory controllers and graphics cores all over the place. The first generation of desktop Nehalem processors will use traditional North Bridges with the graphics core and the memory controller integrated into them. An exception will be made, however, for server Nehalem processors: they need the integrated memory controller to compete successfully with the AMD Opteron CPUs. Desktop and mobile Nehalem processors will have no integrated memory controller, or will have it disabled. This way we can clearly see that desktop Nehalem processors will use Socket H design, while their server counterparts will work in Socket B. The integrated memory controller is also expected to become an attribute of the Extreme Edition Nehalem processors.

Intel is reported to already have the first samples of Tylersburg chipset for upcoming processors available. At the same time, the first engineering samples of the new Nehalem CPU should be sent out to Intel partners only in October.

Tylersburg chipset will be designed specifically for Nehalem based desktop systems. It will be more economical and will have more PCI Express lines. The chipset will support new series processor bus aka CSI with point-to-point topology, which will be introduced in the future generation Intel processors.
 
Intel's next-generation 45nm Hi-k microarchitecture (code named "Nehalem") is the first truly dynamic and design-scalable microarchitecture that will deliver both performance on demand and optimal price/performance/energy efficiency for mobile, desktop, and server platforms.

Dynamically scalable for maximum performance on demand with energy efficiency:

• Dynamically managed cores, threads, cache, interfaces, and power
• Leverages four-instruction issue Intel Core microarchitecture
• Simultaneous multithreading to enhance performance and energy efficiency
• New Streaming SIMD Extensions 4 (SSE4) and ATA instruction set architecture additions
• Multi-level shared cache leverages Intel Smart Cache
• Increased system and memory bandwidth
• Performance enhanced dynamic power management

Design scalable for optimal price/performance/energy efficiency in each market segment:

• New system architecture for next-generation Intel processors and platforms
• Scalable performance: 1 to 16+ threads, 1 to 8+ cores, scalable cache sizes
• Scalable and configurable system interconnects and integrated memory controllers
• High-performance integrated graphics engine for client