Samsung Electronics, the world’s largest producer of memory, has announced that it had begun mass producing the industry’s first 1Gb DDR2 DRAM (dynamic random access memory) using 60nm process technology.

Ample market availability of 1Gb DRAM will further increase the demand for large density DRAMs, especially as the new premium Vista operating system imposes a DRAM requirement of at least 1GB. Samsung’s lineup of 60nm 1Gb DRAM-based modules includes 512MB, 1GB, and 2GB densities supporting either 667MHz or 800MHz speeds with customer validation.

Samsung anticipates such a high degree of receptivity to the 60nm process that it should drive greater demand for 1Gb DRAM chips in the near future over today’s mainstream density of 512Mb.

According to Samsung, 60nm process technology increases production efficiency by 40% over the 80nm process technology deployed in DRAM fabrication since early 2006, and offers twice the productivity of 90nm process technology.

Samsung’s continuous technology migration below 90nm has relied heavily on the company’s use of three-dimensional (3D) transistor technologies to build increasingly smaller chips.  One of the key technologies involved in the development of Samsung’s 3D transistor is a recess channel array transistor (RCAT) that actually builds the DRAM cell three-dimensionally to minimize its size while increasing its density.

Samsung’s proprietary RCAT technology was first introduced at the 2003 VLSI symposia. This new 3D transistor technology doubles the refresh cycle, which is critical for enabling efficient fabrication on a nanometer-scale. Samsung has been utilizing RCAT for DRAM fabrication from 90nm. This key 3D technology is expected to enable DRAM fabrication to 50nm and lower.

In addition to its 60nm process technology innovation, Samsung’s use of metal-insulator metal (MIM) for its capacitors provides enhanced data storage in sub-70nm designs.

Furthermore, the use of a recently-announced selective epitaxial growth (SEG) technology provides for a broader electron channel, and optimizes the speed of each chip’s electrons to reduce power consumption and enable higher performance.

The 60nm process is expected to become the mainstream circuit technology for DRAM in 2008. In the first year of market availability alone, 60nm DRAM revenues are expected to reach $2.3billion worldwide and further increase to $32 billion by 2009.