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Synopsys, a company that develops and sells integrated circuit (IC) design software, announced that ATI Research, a subsidiary of ATI Technologies, has adopted Synopsys’ DFT Compiler SoCBIST to implement the design-for-test architecture for its upcoming next-generation visual processor.

SoCBIST is an extension to DFT Compiler, a key component of Synopsys' Galaxy Design Platform. According to IC design software vendor, ATI is able to improve test quality and reduce test cost for one of their most important designs. Based on the facts stated by both companies we can figure out that everything is about ATI’s code-named R400 VPU due to be launched sometimes later. Furthermore, companies shed some light on the design of the novelty.

It is said that ATI’s [next-generation] visual processing unit (VPU) has more than 200 million transistors of digital logic. A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.13 micron process geometries and below. Using basic scan methods, excellent delay test requires up to 6X more tester time than required for stuck-at faults, which already is at an unacceptable cost of test. ATI and Synopsys claim that SoCBIST software will significantly reduce testing costs while still maintaining the highest possible quality of the test.

I have no idea about the time that will take ATI to test its next-generation graphics processor made using 0.13 micron technology, however, I can state for sure that the major improvement of ATI R300 architecture will for sure not be here for at least a quarter or two. In fact, we already reported that ATI’s David Orton proclaimed 24 months architecture cycles for graphics processors, so, we can even speculate that the code-named R400 part will only emerge in July 2004, roughly 24 months after the original R300 was announced. Well, I doubt that it will take ATI so long to test the next-generation VPU, hence, it is logical to expect R400 appearance earlier than that. But when?

Discussion

Comments currently: 1
Discussion started: 05/24/03 01:02:27 PM
Latest comment: 05/24/03 01:02:27 PM

[1-1]

1. 
Design for Test is the insertion of test structures in the description of an integrated ciruit in order to ease detection of defective circuits after production.

"Test" phase is done at the end of the production line, and it is wrong to state that it is part of the conception flow. At the contrary, Design for Test (DFT) is a part of design phase.
[Posted by: davFR  | Date: 05/24/03 01:02:27 PM]

[1-1]

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